Currently, virtual machines have been applied widely, and interrupts often occur in the application of the virtual machines. For example, when multiple tasks run and are not bound in a symmetrical multi-processing (SMP) system, interrupts, for example, inter-processor interrupts (IPI) occur frequently due to load balancing scheduling, and certainly there may be other interrupts. However, the interrupts are all implemented by accessing a register of an advanced programmable interrupt controller (APIC). A specific implementation process is as follows:
reading a delivery status value in a virtual interrupt command register (vICR) of the APIC;
writing an identifier of a target virtual central processing unit local APIC (vLocal APIC) into a high-order register of ICR according to the delivery status value; and
writing indication data used to indicate that an interrupt occurs on a target virtual central processing unit (vCPU) to which the target vLocal APIC belongs into a low-order register of the ICR, so that a virtual machine monitor (VMM) obtains, by means of parsing, the foregoing identifier registered on the high-order register of the ICR, obtains, by means of parsing, indication data registered on the low-order register of the ICR, and forwards the identifier and the indication data to the target vLocal APIC. When receiving the foregoing information, the target vLocal APIC may control the target vCPU to generate an interrupt.
It can be learned that, in the foregoing interrupt implementation process, it is required to perform operations on the APIC three times, that is, three times of virtual machine exits (VM-Exit) are caused, where a VM-Exit may specifically be understood as a context switching between the virtual machine and a Hypervisor. However, in an actual application, interrupts occur frequently on the virtual processor, which means that the VM-Exits occur on the virtual machine more frequently; as a result, performance of the virtual machine deteriorates.